The term “device under test” or DUT commonly refers to a logic circuit that a test system analyzes or tests to determine the electrical characteristics thereof. For example, a DUT such as a processor may include multiple data receivers that an engineer, technician or other user desires to characterize. The process of characterizing circuit structures such as data receivers includes testing those structures to determine compliance with acceptable operating parameters. These operating parameters may include the input signal shape, signal amplitude, signal width, frequency and response time.
A processor DUT may include data transmitters as well as data receivers. The data transmitters transmit information from the DUT to circuits external to the DUT, while the data receivers receive data from circuits external to the DUT. As the frequencies that a DUT employs become higher and higher with the advance of technology, the testing of circuit structures such as data receivers becomes more difficult. “External I/O wrap” is one technique for characterizing the data receivers of a DUT. The external I/O wrap technique involves the data transmitters of the DUT generating a high speed data pattern that loops back to the data receivers of the DUT. Unfortunately, with the I/O wrap technique the tester can not determine if a data error originates with one of the data transmitters or one of the data receivers. “Internal I/O wrap” is another technique for characterizing the data receivers of the DUT. The internal I/O wrap methodology involves sending a data pattern into the data receivers of the DUT and looping the data pattern inside the DUT to the data transmitters. The data transmitters then transmit the data pattern. A tester couples to the data transmitters to check for errors. Unfortunately, once again a tester can not determine if a data error originates from one of the data receivers or one of the data transmitters.
A combined external wrap/cyclic redundancy check (CRC) approach provides yet another technique for characterizing DUT components such as DUT data receivers and data transmitters. In this technique, the data transmitters send a high speed data pattern together with a CRC code that the data receivers receive. A tester then tests the received data pattern. Unfortunately, with this approach you can generally not determine which particular receiver of the data receivers, or which particular transmitter of the data transmitters, failed. Some DUT systems may employ a trace logic analyzer for debugging purposes.
What is needed is a method and apparatus that tests a DUT with a high speed data pattern and that addresses the above problems.